1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more specifically, to a semiconductor integrated circuit device composed of CMOS transistors and bipolar transistors.
2. Description of the Related Art
(1) FIG. 45 shows an example of an integrated injection logic (IIL) circuit such as, disclosed in the text "Integrated Circuit Engineering" (2), page 88, published by Corona Co., Ltd. in 1979. The IIL circuit is composed of a lateral PNP transistor Q3, and NPN transistors Q1 and Q2 each having an emitter and collector disposed at reverse positions in the structure thereof (hereinafter, referred to be reversely connected) as compared with those of a usual vertical type NPN transistor. The emitter of the PNP transistor Q3 is referred to as an injector, and when a positive voltage is applied to the injector, an injection current flows. When a terminal X1 is opened (turned OFF), the injection current serves as a base current of the reversely connected NPN transistor Q1 and thus the NPN transistor Q1 is turned ON. Therefore, a terminal Y1 is at a potential V.sub.CE (sat) and goes to a low level.
Conversely, when the terminal X1 is short circuited to a ground potential (turned ON), the injection current serves as the collector current of a transistor at a previous stage and the NPN transistor Q1 is turned OFF. The collector of the NPN transistor Q1 is connected to the base of a transistor at a next stage and the transistor at the next stage is turned ON, and thus the terminal Y1 goes to a potential V.sub.be or a high level. When the NPN transistor Q2 is turned ON, however, the terminal Y1 is at the potential V.sub.CE (sat) or at the low level.
On the other hand, when the injection current flows and a terminal X2 is opened (turned OFF), the injection current serves as the base current of the reversely connected NPN transistor Q2 and the NPN transistor Q2 is turned ON. Therefore, the terminals Y1 and Y2 goes to the potential V.sub.CE (sat) or the low level.
Conversely, when the terminal X2 is short circuited to the ground potential (turned ON), the injection current serves as the collector current of the transistor at the previous stage and the NPN transistor Q2 is turned OFF. The collector of the NPN transistor Q2 is connected to the base of the transistor at the next stage and the transistor at the next stage is turned ON, and thus the terminals Y2 and Y1 go to a base to emitter potential V.sub.be or the high level. When the NPN transistor Q1 is turned ON, however, the terminal Y1 goes to the collector voltage V.sub.CE (sat) or the low level. That is, the potential at the terminal Y1 is obtained by ANDing the inverted potential at the terminal X1 and the inverted potential at the terminal X2, and the potential at the terminal Y2 is the inverted potential of the potential at the terminal X2.
Further, FIG. 46 shows an IIL circuit as a conventionally proposed logic circuit (e.g., inverter circuit) suitable for a low voltage. In FIG. 46, a power supply voltage (hereinafter, referred to as V.sub.cc) is sufficient to be a built-in potential (hereinafter, referred to as V.sub.BE) between the emitter and the base of a PNP bipolar transistor 1, i.e., about 0.8 V and thus this circuit is very suitable for a low voltage.
(2) FIG. 47 shows an example of the inverter circuit of a non-threshold logic (NTL) circuit, which is composed of an initial stage including resistors R1, R2, a capacitor C1 and NPN transistor Q1 and of an emitter follower stage including an NPN transistor Q2 and a resistor R3. A power supply terminal 282 has a potential of -2 V. When an input 280 is at a high level (-0.8 V), the NPN transistor Q1 is turned ON, a current flows from a ground potential to the power supply terminal through the resistor R2, NPN transistor Q1 and resistor R1. As a result, the collector potential of the NPN transistor Q1 drops. The values of the resistors R1 and R2 are usually set so that a potential drop is about 0.8 V. The potential dropped from the collector potential by the potential between the base and the emitter of the NPN transistor Q2 is the potential of an output 281. The potential of the output 281 is about -1.6 V which is at a low level. On the other hand, when the input 280 is at the low level (-1.6 V), the NPN transistor Q1 is turned OFF and the collector potential of the NPN transistor Q1 is risen substantially to the ground potential. The potential dropped from the collector potential by the voltage V.sub.BE between the base and the emitter of the NPN transistor Q2 is the potential of the output 281. The potential of the output 281 is about -0.8 V which is at the high level.
(3) FIG. 48 shows an example of the inverter circuit of an emitter-coupled logic (ECL) circuit. In the figure, the inverter circuit is composed of a differential amplifier including resistors R1 and R2, NPN transistors Q1 and Q2 and a constant current source 294 and of an emitter follower unit including an NPN transistor Q3 and a resistor R3. The potentials of power supply terminals 292 and 293 are -3 V and -2 V, respectively. A reference potential V.sub.BB which is an intermediate potential (-1.2 V) between a high level (-0.8 V) and a low level (-1.6 V) is applied to the base of the NPN transistor Q2. When an input 290 is at the high level (-0.8 V), the NPN transistor Q1 is turned ON and a current flows from a ground potential to the power supply terminal 292 through the resistor R1, NPN transistor Q1 and constant current source 294. As a result, the collector potential of the NPN transistor Q1 is dropped. The resistance value of the resistor R1 and the current value of the constant current source 294 are usually set so that a potential drop is about 0.8 V. The potential dropped from the collector potential by the voltage V.sub.BE between the base and the emitter of the NPN transistor Q3 is the potential of an output 291 (low level, -1.6 V).
On the other hand, when the input 290 is at the low level (-1.6 V), the NPN transistor Q1 is turned OFF and the collector potential of the NPN transistor Q1 is risen substantially to the ground potential. The potential dropped from the collector potential by the voltage V.sub.be between the base and the emitter of the NPN transistor Q3 is the potential of the output terminal 291. The potential of the output terminal 291 is about -0.8 V which is at the high level.
(4) FIG. 49 shows an inverter circuit as a conventional BiCMOS composite circuit (Japanese Patent Examined Publication Sho 50-40977). The inverter circuit is composed of an NPN transistor 300 and NMOS transistor 301 constituting an output stage, and a PMOS transistor 302 and NMOS transistor 303 controlling the NPN transistor 300 and taking an inverted logic. When the potential at an input terminal 305 is at a low level, the PMOS transistor 302 is turned ON, the NMOS transistor 303 is turned OFF, the NPN transistor 300 is turned ON, and the NMOS transistor 301 is turned OFF. Therefore, the potential of an output terminal 306 is goes to a high level. The potential level at this time is obtained by subtracting the voltage V.sub.BE between the base and emitter of the NPN transistor 300 from the power supply voltage V.sub.cc at a power supply terminal 304.
On the other hand, when the potential at the input terminal 305 is at the high level, the PMOS transistor 302 is turned OFF, the NMOS transistor 303 is turned ON, the NPN transistor 300 is turned OFF, and the NMOS transistor 301 is turned ON. Therefore, the potential of the output terminal 306 goes to the low level which is a ground potential.
(5) FIG. 50 shows an example of an inverter circuit as a conventional BiCMOS composite circuit (Japanese Patent Unexamined Publication Sho 62-281614). In the figure, the inverter circuit is composed of NPN transistors 310 and 311 constituting a totem-pole output stage; a PMOS transistor 312 and NMOS transistor 313 controlling the NPN transistor 310 and the like and taking an inverted logic; a PMOS transistor 314 having a source connected to a power supply terminal 318, a drain connected to the source of a PMOS transistor 315, and a gate connected to the base of the NPN transistor 310, respectively; the PMOS transistor 315 having a gate connected to the output terminal of a CMOS inverter 317 the input of which receiving a signal from an output terminal 320, and a drain connected to the base of the NPN transistor 311, respectively; and an NMOS transistor 316 having a drain connected to the base of the NPN transistor 311, a gate connected to the base of the NPN transistor 310, and a source connected to a ground potential.
In the above arrangement, when the potential of an input terminal 319 is at a low level, the PMOS transistor 312 is turned ON, the NMOS transistor 313 is turned OFF, the NPN transistor 310 is turned ON, the PMOS transistor 314 is turned OFF, the NMOS transistor 316 is turned ON, and the NPN transistor 311 is turned OFF. Therefore, the potential of the output terminal 320 goes to a high level. The potential of the output terminal 320 at this time is obtained by subtracting the voltage V.sub.BE between the base and the emitter of the NPN transistor 310 from the power supply voltage V.sub.cc level of the power supply terminal 318.
On the other hand, when the potential of the input terminal 319 goes to the high level, the PMOS transistor 312 is turned OFF, the NMOS transistor 313 is turned ON, and the NPN transistor 310 is turned OFF. Further, since the NMOS transistor 316 is turned OFF, the PMOS transistor 314 is turned ON, and the PMOS transistor 315 is turned ON, a base current is supplied to the NPN transistor 311 to thereby turn ON the NPN transistor 311. Therefore, the potential of the output terminal 320 goes to a low level. When the output goes to the low level, the PMOS transistor 315 is turned OFF, and thus the excessive saturation of the NPN transistor 311 can be prevented without flowing an excessive current to the base of thereof. The low level at this time is substantially equal to a ground potential.
(6) Although a BiCMOS logic gate is mixed with a CMOS logic gate in a conventional BiCMOS composite LSI, when an NTL logic gate is tried to be mixed therewith, a level conversion circuit is necessary between the NTL logic gate and the BiCMOS logic gate or between the NTL logic gate and the CMOS logic gate.
(7) An ECL circuit composed of bipolar transistors, a BiCMOS circuit composed by combining PMOS transistors and NMOS transistors and bipolar transistors and a CMOS circuit composed of PMOS transistors and NMOS transistors are conventionally used as a logic gate circuit. Respective circuit systems are applied to these logic gate circuits in correspondence With the performances such as high speed property, low power consumption property, high integration property and the like.
On the other hand, recently, as semiconductor devices are miniaturized, a requirement for lowering a power supply voltage supplied to an integrated circuit, on which the miniaturized semiconductor devices are mounted, is rapidly increased. When this low power supply voltage is taken into consideration, a CMOS circuit is superior to the circuit composed of bipolar transistors in a low power operating property.
FIG. 57 shows an inverter circuit using a CMOS circuit, wherein the CMOS inverter circuit is arranged such that a pair of a PMOS transistor 563 and NMOS transistor 564 are connected in series to perform a complementary operation.
(8) Recently, as semiconductor integrated devices are miniaturized, a requirement for lowering a power supply voltage supplied to the integrated circuits is increased. A BiMOS circuit composed of a bipolar transistor and MOS transistor in combination to increase an operation speed and lower a power consumption begins to cope with this requirement. When this low voltage operation is taken into consideration, it is important in the BiCMOS circuit that an output signal is fully swung between a ground level and a power supply voltage level in order to effectively apply a drive voltage to a next stage.
This is because when the transistor at the next stage is composed of a MOS transistor, it cannot be driven unless a voltage equal to or higher than a threshold voltage V.sub.th is applied between the gate and the source thereof, and when the transistor at the next stage is composed of a bipolar transistor, it cannot be driven unless a voltage equal to or higher than a voltage V.sub.BE between a base and an emitter is applied between the emitter and the base thereof, and an input voltage to the next stage, which is at a power supply potential--a low level (hereinafter, referred to as "L")--and at a high level (hereinafter, referred to as "H")--a fixed potential--, must be secured in a value as large as possible.
FIG. 76 shows an example of an integrated circuit device in which the low power operation is partially taken into consideration (Japanese Patent Unexamined Publication Sho 62-281614). FIG. 76 shows the arrangement of an inverter circuit. The operation of the inverter circuit will be simply described. When an input 811 is at an "H" level, an NMOS transistor 815 is turned ON, the drain of the NMOS 815 Goes to an "L" level, and a PMOS transistor 841 is turned ON. At this time, an "H" level signal before the potential of an output terminal 813 shifts to the "L" level is inverted by a CMOS inverter 844 composed of a PMOS transistor 821 and NMOS transistor 822, and thus a PMOS transistor 842 is turned ON. As a result, the potential of a power supply terminal 810 is applied to the base of an NPN transistor 824 through the PMOS transistors 841 and 842, and thus the potential of the output terminal 813 shifts to the "L" level.
The potential of the output terminal 813 completely drops to the same potential as that of a fixed potential terminal (ground terminal) because the NPN transistor 824 has a base potential higher than a collector potential and is saturated in a forward bias and thus a voltage V.sub.BE between a base and emitter is extinguished. In this case, as the NPN transistor 824 is more deeply saturated, a longer time is required for the potential of the output terminal 813 to be shifted and thus a high speed operation is disturbed thereby. To prevent this phenomenon, the gate of the PMOS transistor 842 is turned OFF in such a manner that a signal which is at the "L" level at the output terminal 813 is inverted by the CMOS inverter 844 composed of the PMOS transistor 821 and NMOS transistor 822 to thereby turn OFF the gate of the PMOS ttt 842, whereby a power supply terminal voltage to the gate of the NPN transistor 824 is shut off.
On the other hand, when the potential of the input terminal 811 is at the "L" level, the PMOS transistor 814 is turned ON and the NMOS transistor 815 is turned OFF, and thus the drain of the PMOS transistor 814 goes to the "H" level to cause the NMOS transistor 843 to be turned ON and the NPN transistor 824 to be turned OFF as well as the NPN transistor 823 to be turned ON. As a result, the potential of the output terminal 813 goes to the "H" level. The potential of the output terminal 813 at this time is lower than the power supply voltage by the voltage V.sub.BE between the base and the emitter of the NPN transistor 823, because the NPN transistor 823 has the same base potential as that of the power supply terminal 810 since the PMOS transistor 814 is turned ON.
As described above, the circuit shown in FIG. 76 is arranged such that when the output terminal 813 is at the "L" level, the output terminal 813 can be lowered to the fixed terminal potential (ground level) and thus the circuit can be said to aim at operation at a lower voltage.
(9) Conventionally, there is known a BiCMOS circuit composed by the combination of a bipolar transistor and MOS transistor as the inverter circuit of a logic circuit. According to this circuit, a speed can be increased by the bipolar transistor and a power consumption can be reduced by the MOS transistor. Japanese Patent Unexamined Publication No. Sho 57-212827, for example, discloses this kind of an inverter circuit.
On the other hand, as a semiconductor integrated circuit device is miniaturized, it is recently required to drop a power supply voltage to be supplied to an integrated circuit. For the operation of a circuit at a lower power supply voltage, it is important in the BiCMOS circuit that an output signal is fully swung to effectively apply a drive voltage to a logic circuit of a next stage, i.e. to swing a signal in a full power supply range. This is because that when a signal is output to the logic circuit of the next stage, if the logic circuit of the next stage is composed of a MOS transistor, the logic circuit cannot be operated unless a voltage equal to or higher that a voltage between a gate and a source is applied, and if it is composed of a bipolar transistor, the logic circuit cannot be operated unless a voltage equal to or higher that a voltage between a base and an emitter is applied. Thus, even if the bipolar transistor is simply turned ON and OFF, an output voltage is dropped by the voltage between the base and the emitter and a fully swung signal cannot be output. As a result, the transistor must be operated to be temporarily saturated to fully swing the signal.
(1) First, the above prior art has a problem that a gate circuit has a slow speed, because transistors Q1 and Q2, in FIG. 45, are each composed of an NPN transistor having a collector and emitter formed reversely as compared with a usual vertical type transistor and thus a gate circuit has a slow speed. Next, the prior art has a problem that an injection current value is not effectively used at all times. That is, when the reverse type NPN transistor is turned ON to drop a collector potential and even after the collector potential has been dropped, the injection potential flows as a collector potential. At this timing, the injection potential is not necessary. Therefore, a power consumption and gate propagation delay time are increased. Further, when a base current is risen, the injection current flows as a base current even after the base current has been risen. Therefore, the reversely connected NPN transistor is deeply saturated, and thus the gate propagation delay time and power consumption are increased.
Further, the illustrated prior art IIL circuit (FIG. 46 shows an IIL inverter of two stages) has the following problem in operation. When an input is at a high level potential, an output from a first stage has a low level potential and an output from a second stage, i.e. the circuit output, has a high level potential. At this time, the pull-up PNP bipolar transistor Q11 of the first stage is in an active state and an injection current (hereinafter, referred to as Ij) mainly flows from a PNP bipolar transistor Q11 (Q12) to an NPN bipolar transistor Q13 (Q14), as shown by the arrow of a dot-dash line in FIG. 46. On the other hand, the PNP bipolar transistor Q12 of the second stage is saturated because the output voltage or the collector voltage thereof goes to the high level voltage, and thus Ij flows from the emitter to the base thereof, as shown by the arrow of a dot-dash line in FIG. 46. As described above, a problem arises in that even if the output of the IIL circuit is at any potential of the high level potential and low level potential, a steady state current Ij exists and a large power consumption is required. The reduction of Ij for solving or mitigating the problem means the delay of the rising-up of an output and thus the delay time of a circuit is increased. Further, the reduction of Ij causes the NPN bipolar transistor Q13 (Q14) to be saturated and thus the rising time is further delayed. As described above, at present, a low power consumption is incompatible with a high speed in the IIL circuit.
(2) In the prior art NTL circuit shown in FIG. 47, the charge and discharge speed of each node may be determined by the time constant of a resistor and parasitic capacitor. Thus, the reduction of a resistance value for increasing a speed results in an increase of a power consumption. That is, either the speed or low power consumption must be selected.
(3) In the prior art ECL circuit shown in FIG. 48, the discharge speed of the output from the emitter follower unit is determined by the time constant of a resistor and parasitic capacitor. Thus, the reduction of a resistance value for increasing a speed results in an increase of a power consumption. That is, either the speed or low power consumption must be selected.
(4) In the prior art BiCMOS composite circuit shown in FIG. 49, the following formula is established. EQU V.sub.IH min=V.sub.th =V.sub.cc min-V.sub.BE
That is, the input voltage V.sub.IH min which can be recognized as a minimum operable logic "1" is equal to the threshold voltage V.sub.th of the NMOS transistor 301 as well as equal to the value obtained by subtracting the voltage between the base and the emitter V.sub.BE of the NPN transistor 300 from a minimum operable power supply voltage V.sub.cc min. Therefore, the minimum operable power supply voltage V.sub.cc min is represented by the following formula. ##EQU1## That is, although this prior art BiCMOS circuit can be operated by a low power supply voltage of 2 V to 1.5 V, a problem arises in that when the potential of an output terminal 306 is at a high level, since it does not fully swing to a power supply voltage V.sub.cc, a problem arises in that a DC current flows at a next stage and the speed of the gate circuit of the next stage is lowered.
(5) In the case of the prior art BiCMOS composite circuit shown in FIG. 50, the following formula is established. EQU V.sub.IH min=V.sub.th =V.sub.cc min-V.sub.BE
That is, the input voltage V.sub.IH min which can be recognized as a minimum operable logic "1" is equal to the threshold voltage V.sub.th of the NPN transistor 313 as well as equal to the value obtained by subtracting the voltage between the base and the emitter V.sub.BE of the NPN transistor 310 from a minimum operable power supply voltage V.sub.cc min. Further, the relationship V.sub.cc min&gt;V.sub.BE must be satisfied in order to that the NPN transistor 311 of the output stage operates. Therefore, the minimum operable power supply voltage V.sub.cc min is represented by the following formula. ##EQU2##
As described above, operation can be performed to a considerable low power supply voltage in spite of that the output stage is composed of the totem-pole connected gate. However, when the potential of an input terminal 319 is at a high level and the potential of an output terminal 320 is at a low level and then a noise is added to the potential of the output terminal 320 and the magnitude of the noise exceeds the logic threshold voltage of a CMOS inverter 317, a base current is supplied to the NPN transistor 311 to try to keep the low level. When, however, the magnitude of the noise is less than the logic threshold voltage, no action is taken to extinguish the noise, and thus this BiCMOS composite circuit has a defect that it is weak to noise.
Further, there is also a defect described by using FIGS. 51 and 52. That is, as shown in FIG. 51, there exists a connection capacitor 321 for the sources or drains of a PMOS transistor 314 and PMOS transistor 315 located therebetween.
Further, there exists a parasitic capacitor 322 such as a base capacitor, the connection capacitor of a PMOS transistor 315 and the like around the base of an NPN transistor 311. FIG. 52 shows an operation timing and the ON/OFF states of respective MOS transistors, wherein a time axis is divided into five regions I-V. A region I represents the state that the potential of an input terminal 319 is set to a low level and the potential of an output terminal 320 is set to a high level. At this time, since the PMOS transistor 314 is turned OFF, the PMOS transistor 315 is turned OFF and an NMOS transistor 316 is turned ON at this time, the potential of an A point is set to the absolute value of the threshold voltage of the PMOS transistor 315 and the base potential of the NPN transistor 311 is set to a ground potential.
A region II represents the state that the potential of the input terminal 319 begins to rise up and the potential of the output terminal 320 begins to fall down. At this time, the PMOS transistors 314 and 315 are turned ON, the NMOS transistor 316 is turned OFF, and the potential of the point A rises according to the time constant determined by the ON resistances of the PMOS transistors 314 and 315 and the like. Further, the base potential of the NPN transistor 311 rises and the NPN transistor 311 is turned ON.
A region III represents the state that the potential of the input terminal 319 is at the high level and the potential of the output terminal 320 is at the low level. At this time, the PMOS transistor 314 is turned 0N and the PMOS transistor 315 and NMOS transistor 316 are turned OFF. The potential of the point A is set to the power supply voltage V.sub.cc of a power supply terminal 318 and the base potential of the NPN transistor 311 is kept to the same potential as the power supply voltage V.sub.cc, but this potential is gradually dropped.
A region IV represents the state that the potential of the input terminal 319 begins to fall down and the potential of the output terminal 320 begins to rise up. At this time, the PMOS transistors 314 and 315 are turned OFF, the NMOS transistor 316 is turned ON, the potential of the point A is kept to the state of the region III, and the base potential of the NPN transistor 311 quickly drops.
A region V represents the state that the input terminal 319 is at the low level and the output terminal 320 is at the high level. At this time, the PMOS transistor 314 is turned OFF, the PMOS transistor 315 is turned ON, and the NMOS transistor 316 is turned ON. Although the potential of the point A reduces towards the absolute value of the threshold voltage of the PMOS transistor 315, the base potential of the NPN transistor 311 increases once and then reduces towards a ground potential. This is caused by the distribution of the charge stored in the parasitic capacitor 321 is distributed to a parasitic capacitor 322 by the turning ON of the PMOS transistor 315. As a result, the NPN transistor 311 is turned ON for a period at the timing when it is to be turned OFF. Thus, a passing-through current flows from the V.sub.cc power supply terminal 318 to a ground potential terminal. This passing-through current causes a power consumption to be increased and a charging current supplied to a load by an NPN transistor 310 also to escape to the NPN transistor 311, and thus a high speed operation is obstructed.
(6) The aforesaid prior art is difficult to utilize the feature of a high speed NTL logic gate due to the delay arisen in a level conversion circuit.
(7) The logic gate circuit using the aforesaid conventional CMOS circuit is excellent in a low power supply voltage property and low power consumption property, whereas it has an increased load dependency of a gate propagating delay time because a PMOS transistor and NMOS transistor are inferior to a bipolar transistor in a current drive capability, and thus a problem remains in the speed of the gate propagation delay time.
(8) In the aforesaid prior art BiCMOS circuit (e.g., FIG. 76), the signal level of the output terminal 813 is dropped to the fixed terminal potential (ground level) only when it is at an "L" level. When, however, the signal level of the output terminal 813 is at the "H" level, the signal does not go to the power supply voltage level of the power supply terminal 810 and goes to the level lower than this level by the voltage V.sub.BE between the base and the emitter of a bipolar transistor 823 and the signal is not fully swung. The signal level of the output terminal 813 must be fully swung in order to realize operation performed at a low voltage.
The base potential of the NPN transistor 823 which is turned ON when the potential of the output terminal 813 is at an "H" level must be higher than the potential of the power supply terminal 810 or the collector potential of the NPN transistor 823 so that the NPN transistor 823 is saturated in the same way as the NPN transistor 824 which is turned ON when the potential of the output terminal 813 is at the "L" level in order that operation is performed with the fully swung signal level of the output terminal 813. For this purpose, the circuit must be arranged to introduce a potential higher than the potential of the power supply terminal 810. Although it may possible to arrange a circuit by using a PNP transistor in place of the NPN transistor 823 going to the H level side, this circuit must be arranged by using the NPN transistor at any risk.
Further, when the NPN transistor 824 going to the "L" level side is turned ON, the base potential thereof is shut off by the PMOS transistor 842, but it is in a saturated region and a recovery time is needed in transition and a problem arises in that high speed operation is obstructed.
In the aforesaid prior art, although a speed is increased and a power consumption is reduced by using an inverter circuit composed of a bipolar transistor and MOS transistor in combination, since the bipolar transistor is not operated in a transitionally saturated state, the feature of the bipolar transistor cannot be sufficiently utilized and thus a sufficient high speed cannot be achieved. Moreover, a PMOS transistor must be connected in series to the bipolar transistor in order to fully swing a signal, which makes a circuit arrangement complex.